I. Field of the Invention
The present invention relates to an improvement in a semiconductor substrate, and a method for manufacturing a semiconductor device using such an improved semiconductor substrate.
II. Description of the Prior Art
In the manufacture of LSIs, and particularly MOSLSIs, cost is an important problem. With increasing demands for lower manufacturing costs, semiconductor substrates (wafers) for LSIs tend to have larger diameters. If a wafer has a larger diameter, a greater number of LSI chips may be formed, resulting in improved mass-production and lower manufacturing costs for semiconductor devices.
However, when the diameter of a wafer is increased but the thickness remains the same, the mechanical strength of the wafer is degraded to cause warpage or deformation during annealing. Therefore, the thickness of the wafer must be increased together with an increase in the diameter. For example, a wafer having a diameter of 2 inches has a thickness of 200 to 300 .mu.m; a wafer having a diameter of 3 inches has a thickness of 350 to 450 .mu.m; a wafer having a diameter of 4 inches has a thickness of 500 to 600 .mu.m; and so on.
When the thickness of the wafer is increased, however, the following problems are encountered:
(1) When the thickness is increased, the wafer can withstand annealing without suffering warpage or the like, but the wafer is then subject to a greater stress, resulting in defects.
(2) After forming a plurality of LSI chips on a wafer, the wafer is made thinner by lapping or the like, and a metal such as Au is deposited on its rear surface to decrease its resistance. If the thickness after lapping is great, the resistance cannot be sufficiently decreased. On the other hand, if lapping is performed to make a thick and large diameter wafer sufficiently thin, the wafer may crack during lapping.
(3) If the wafer is thick, it is also heavy. Then, when it is placed in a rotator for drying, the centrifugal force on the wafer is increased and the wafer may not be stably supported.
An increased wafer thickness not only affects the wafer but also the manufacturing steps of, for example, MOS transistors as will be described below.
FIG. 1 is a sectional view of a MOS transistor in an intermediate manufacturing step (after forming contact holes and before phosphorus gettering). The MOS transistor has a silicon semiconductor substrate (wafer) 1 of p-conductivity type. N.sup.+ -type source and drain regions 5 and 6 are electrically isolated from each other and are formed in an island region isolated by a field oxide film 2 formed on the wafer 1. A gate electrode 3 of polycrystalline silicon is formed through a gate oxide film 4 on a surface portion of the wafer 1 between the source and drain regions 5 and 6. An interlayer insulating film 7 such as a CVD-SiO.sub.2 film is formed on the entire surface of the substrate 1 including the surface of the gate electrode 3. Contact holes 8 are formed in the portions of the interlayer insulating film 7 corresponding to the source and drain regions 5 and 6. After obtaining the structure as described above, gettering using phosphorus (hereinafter referred to as "phosphorus gettering") is performed from a rear surface 1a of the wafer and an aluminum wiring is formed, thus completing the main steps for manufacturing MOSLSI's. In the step of phosphorus gettering, heavy metals present in the MOS transistor region are gettered. If the heavy metal is present in the element formation region, problems occur such as an increase in the leakage voltage at a p-n junction, a short life of minority carriers which causes disappearance of a charge stored on an MOS capacitor within a short period of time, and the like.
In the step of phosphorus gettering, phosphorus is diffused into the rear surface of a wafer in a high-temperature atmosphere containing oxygen, so as to form a phosphosilicate glass (PSG) film. During annealing such as the thermal diffusion of the phosphorus, the heavy metal or the like diffused from the element region is fixed in the PSG film, thus removing the heavy metal from the element formation region. However, with an increase in the thickness of the wafer, the time required for the heavy metal to migrate from the element formation region to the rear surface of the wafer is increased, and the efficiency of phosphorus gettering is degraded. Similar problems are encountered when defects are deliberately formed in the rear surface of the wafer, and the contaminant impurities are removed by being trapped by the defects upon annealing. The decrease in the efficiency of gettering is more pronounced when the gettering step is performed at a lower temperature.